1. Field of the Invention
The present invention relates to a flat panel display device, and more particularly, to an active matrix-type liquid crystal display device and a method of driving the same.
2. Discussion of the Related Art
Cathode ray tube (CRT) devices have been commonly used for display devices, such as a television and a monitor. However, the CRT devices have some disadvantages, such as heavy weight, large volume, and high driving voltages. Accordingly, flat panel display (FPD) devices, such as liquid crystal display (LCD) devices and organic electroluminescent display (ELD) devices, are being developed, and have excellent operational characteristics, such as light weight and low power consumption. These devices are commonly used in notebook computers, office automation apparatus, and audio/video apparatus.
In general, an LCD device is a non-emissive display device that displays images by making use of a refractive index difference utilizing optical anisotropy properties of a liquid crystal material interposed between an array substrate and a color filter substrate. On the other hand, an ELD device is an emissive display device making use an electroluminescent (EL) phenomenon, wherein light is emitted from a luminescent layer when an electric field is applied.
Recently, active matrix-type display devices in which a plurality of pixel regions are disposed in matrix and a switching element, such as a thin film transistor (TFT), is formed at each pixel region, are commonly being used because of their superior display of moving images.
FIG. 1 is a schematic block diagram of a liquid crystal display device according to the related art. In FIG. 1, RGB data and timing sync signals, such as clock signals, horizontal sync signals, vertical sync signals, and data enable signals, are input from a driving system (not shown), such as a personal computer, to an interface 10. The interface 10 outputs the RGB data and the timing sync signals to a timing controller 12. For example, a low voltage differential signal (LVDS) interface and TTL interface may be used for transmission of the RGB data and the timing sync signals. In addition, the interface 10 may be integrated in a single chip together with the timing controller 12. The timing controller 12 generates data control signals for a data driver 18, including a plurality of data integrated circuits (ICs), and gate control signals for a gate driver 20, including a plurality of gate ICs. Moreover, the timing controller outputs data signals to the data driver 18.
Reference voltage generator 16 generates reference voltages of a digital-to-analog converter (DAC) used in the data driver 18. The reference voltages are set up according to transmittance-voltage characteristics of a liquid crystal panel 2. The data driver 18 determines reference voltages for the data signals according to the data control signals and outputs the determined reference voltages to the liquid crystal panel 2 to adjust a rotation angle of liquid crystal molecules. The gate driver 20 controls ON/OFF operation of thin film transistors (TFTs) in the liquid crystal panel 2 according to the gate control signals from the timing controller 12. Accordingly, the data signals from the data driver 18 are supplied to pixels of the liquid crystal panel 2 through the TFTs. Source voltage generator 14 supplies source voltages to elements of the LCD device and a common voltage to the liquid crystal panel 2.
FIG. 2 is a schematic block diagram of a timing controller for a liquid crystal display device according to the related art. In FIG. 2, a timing controller 12 includes a control signal generator 36, a data signal generator 32, and a signal discriminating portion 28. The control signal generator 36 generates data control signals and gate control signals by using timing sync signals, such as a horizontal sync signal “Hsync,” a vertical sync signal “Vsync,” a data enable signal “DE,” and a clock from an interface 10 (in FIG. 1), and supplies the data control signals and the gate control signals to a data driver 18 (in FIG. 1) and a gate driver 20 (in FIG. 1). The data signal generator 32 generates data signals by using RGB data from the interface 10 (in FIG. 1) and supplies the data signals to the data driver 18 (in FIG. 1). The signal discriminating portion 28 determines whether all of the RGB data and the timing sync signals are supplied from the interface 10 (in FIG. 1). In addition, an oscillator 26 supplies reference signals of a specific frequency to the signal discriminating portion 28.
FIG. 3 is a schematic timing diagram of timing sync signals for a timing controller according to the related art. In FIG. 3, a vertical sync signal “Vsync” corresponds to a time interval for one frame and a horizontal sync signal “Hsync” corresponds to a time interval for one gate line. Accordingly, the horizontal sync signal “Hsync” includes peaks corresponding to the number of gate lines in a liquid crystal panel 2 (in FIG. 1). A data enable signal “DE” corresponds to a time interval for supplying data signals to pixels of the liquid crystal panel 2 (in FIG. 1). The data enable signal “DE” includes a first time interval and a second time interval. Accordingly, the data signals are supplied to the pixel during the second time interval, while no data signals are supplied to pixels during the first time interval. In the second time interval, the data enable signal “DE” includes a plurality of peaks “P.”
A control signal generator 36 (in FIG. 2) supplies data control signals and gate control signals to data driver 18 (in FIG. 1) and gate driver 20 (in FIG. 1), respectively, according to the vertical sync signal “Vsync” and the horizontal sync signal “Hsync” from an interface 10 (in FIG. 1). In addition, a data signal generator 32 (in FIG. 2) supplies the data signals to the pixels through the data driver 18 (in FIG. 1) according to the data enable signal “DE” from the interface 10 (in FIG. 1).
FIG. 4 is a schematic timing diagram of output signals of a timing controller according to the related art. In FIG. 4, output signals of a timing controller 12 (in FIG. 1) include a gate output enable signal “GOE,” a gate shift clock “GSC,” a source output enable signal “SOE,” a gate start pulse “GSP,” and a polarity reverse signal “POL.” Although not shown in FIG. 4, a source sampling clock “SSC” and a source start pulse “SSP” may be output from the timing controller 12 (in FIG. 1).
Data signals are latched according to a rising edge or a falling edge of the source sampling clock “SSC,” and the source output enable signal “SOE” controls a transmission of the data signals latched by the source sampling clock “SSC” to a liquid crystal panel 2 (in FIG. 1). The source start pulse “SSP” assigns a starting point of one horizontal line (gate line), i.e., a first pixel that the data signals are inputted. The gate shift clock “GSC” assigns a time interval for ON state of a thin film transistor (TFT) and the gate output enable signal “GOE” controls an output of a gate driver 20 (in FIG. 1). The gate start pulse “GSP” assigns a starting line of one frame, i.e., a first line that gate signals are input. The polarity reverse signal “POL” adds one of positive polarity (+) and negative polarity (−) to the data signals during an inversion driving method, such as a dot inversion method. A data signal generator 32 (in FIG. 2) re-arranges RGB data transmitted from an interface 10 (in FIG. 1) and supplies the re-arranged RGB data, i.e., the data signals to the liquid crystal panel 2 (in FIG. 1), through a data driver 18 (in FIG. 1).
FIGS. 5A to 5E are schematic transitional images between frames in a liquid crystal display device according to the related art. FIG. 5A shows a first image of a first frame, FIG. 5E shows second image of a second frame following the first frame. In addition, FIGS. 5B, 5C, and 5D show a mixed image at one, two, and three quarters of one frame time, respectively.
In FIGS. 5A to 5E, most of the second frame time is used for rendering the second image. For example, the second image may be rendered during a time interval more than about 90% of the second frame time. During a refresh driving method of an XGA (1024×768) at 75 Hz, one frame time is about 16 ms and a total number of scan lines (gate lines) is about 800 for one frame. Among the scan lines, about 768 lines are substantially used for displaying images, and are commonly referred to as active lines. Thus, an active time interval for writing images to the active lines is about 15.35 ms (i.e., 16 ms×(768/800)), and this value corresponds to about 96% of one frame time. Accordingly, most of one frame time is used for rendering an image. As shown in FIG. 3, the percentage of the second time interval of the data enable signal “DE” (in FIG. 3) to the sum of the first and second time periods may be more than about 96%.
In FIGS. 5A to 5E, an image is changed from rectangular shape to triangular shape. After completing the first image of rectangular shape, data signals for the second image of triangular shape are written in a liquid crystal panel on a line-by-line basis with the passage of time. The arrows in FIGS. 5B to 5E designate a scan line I which the data signals are written at the corresponding time. In other words, the mixed image of the first and second images is displayed during most of one frame time.
The above-described driving method is suitable for the CRT devices, in which an electron beam instantly collides with fluorescent material of a screen. However, in active matrix-type LCD devices, the data signals may be stored in each pixel during one frame time and the stored data signals may continue driving liquid crystal molecules until the next data signals are written. When the LCD devices are driven using the above-described driving method, wherein most of one frame time is used for rendering an image, excessive time is used for rendering the image. Accordingly, an undesirable mixed image is excessively displayed.